Product Summary
High Capacity
? Single-Chip ASIC Alternative
? 3,000 to 54,000 System Gates
? Up to 2.5 kbits Configurable Dual-Port SRAM
? Fast Wide-Decode Circuitry
? Up to 202 User-Programmable I/O Pins
High Performance
? 5.6 ns Clock-to-Out
? 250 MHz Performance
? 5 ns Dual-Port SRAM Access
? 100 MHz FIFOs
? 7.5 ns 35-Bit Address Decode
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![]() A42MX09-PQ100 |
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![]() IC FPGA MX SGL CHIP 14K 100-PQFP |
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![]() A42MX09-PQ100A |
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![]() IC FPGA MX SGL CHIP 14K 100-PQFP |
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![]() A42MX09-PQ100I |
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![]() IC FPGA MX SGL CHIP 14K 100-PQFP |
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![]() A42MX09-PQ100M |
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![]() IC FPGA MX SGL CHIP 14K 100-PQFP |
![]() Data Sheet |
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